1. Field of the Invention.
The present invention relates to a semiconductor device having a cell transistor with recess channel structure and a method of manufacturing the same. Particularly, the present invention relates to semiconductor device having: a cell transistor with recess channel structure; a peripheral transistor having an nMOSFET structure with a gate electrode containing n-type polysilicon; and a peripheral transistor having a PMOSFET structure with a gate electrode containing p-type polysilicon.
2. Related Art
FIG. 1 is a schematic cross-sectional view illustrating substantial parts of a conventional semiconductor device.
FIG. 1 shows a semiconductor device 100 having a transistor 200 which has an nMOSFET structure where a gate electrode 6a including an N-type polysilicon layer 600 is formed on a P-type semiconductor silicon substrate 1 and a transistor 201 which has a pMOSFET structure where a gate electrode 6b including a P-type polysilicon layer 601 is formed on an N-type well region 360.
The above-mentioned transistor 200 has the gate electrode 6a formed on the semiconductor silicon substrate 1 via a gate insulating film 5 and a pair of source/drain regions 3 corresponding to the gate electrode 6a. 
The gate electrode 6a has the N-type polysilicon layer 600 and a metal silicide 7. Provided on the upper portion and at the both sides of the gate electrode 6a are insulating films 8 and 9, respectively, made of silicon nitride.
In addition, the transistor 201 has, like the transistor 200, the gate electrode 6b formed on the N-type well region 360 in the semiconductor silicon substrate 1 via a gate insulating film 5 and a pair of source/drain regions 4 corresponding to the gate electrode 6b. 
The gate electrode 6b has the P-type polysilicon layer 601 and a metal silicide 7. Provided on the upper portion and at the both sides of the gate electrode 6b are insulating films 8 and 9, respectively, made of silicon nitride.
Further, the transistor 200 and the transistor 201 are separated by a device separation portion 2.
Combination of these transistors is generally called “Complementary MOS” (hereinafter referred to as “CMOS”).
The source/drain region 3 corresponding to the transistor 200 includes N-type impurities and the source/drain region 4 corresponding to the transistor 201 includes P-type impurities.
The transistor of which the conductivity type of the impurities contained in the gate electrode matches the conductivity type of impurities contained in the source/drain region as described above is called “surface channel transistor”.
In the semiconductor device 100 having the CMOS structure as illustrated in FIG. 1, the transistors 200 and 201 are both configured of surface channel transistors (see Japanese patent application publication No. 11-307729).
Meanwhile, FIG. 2 is a schematic cross-sectional view illustrating substantial parts of another conventional semiconductor device.
FIG. 2 illustrates a semiconductor device 101 having a transistor 202 having a pMOSFET structure where a gate electrode 611 including a P-type polysilicon layer is formed on an N-type epitaxial layer 1b, a transistor 203 having an nMOSFET structure where a gate electrode 612 including a P-type polysilicon layer is formed on a P-type well region 340, and a transistor 204 having a pMOSFET structure where a gate electrode 204 including a P-type polysilicon layer 610 with a recess channel structure is formed on the P-type well region 340.
Source/drain regions 301 corresponding to the transistor 202 are formed of P-type high-concentration impurity layers on the surface of the N-type epitaxial layer 1b provided on the semiconductor silicon substrate 1a. 
Further, deposited along with the source/drain regions 301 are P-type low-concentration impurity layers 310.
Besides, source/drain regions 302 corresponding to the transistor 203 are formed of N-type high-concentration impurity layers on the surface of the P-type well region 340.
Further, deposited along with the source/drain regions 302 are N-type low-concentration impurity layers 320.
The transistor 204 has a recess channel structure, however, the source/drain regions 303 corresponding to the transistor 204 are formed of P-type high-concentration impurity layers on the surface of the N-type body regions 341.
Further, deposited along with the source/drain regions 303 are P-type low-concentration impurity layers 330.
The N-type body regions 341 are formed inside the P-type well region 340, and a P-type buried layer 370 is formed at the lower portion of the P-type well region 340.
Further, the recess channel structure is made of insulating films 9, a P-type polysilicon layer 610 and a conducting layer 700, and provided on the upper face of and on the side faces of the conducting layer 700 are insulating films 800 and 9, respectively made of silicon nitride.
In addition, the transistors 202, 203 and 204 are separated from each other by the device separation portions 2.
As described above, the transistor 202 is a surface channel transistor as the gate electrode 611 includes the P-type polysilicon layer and the source/drain regions 301 corresponding to PMOSFET structure contains P-type impurities.
On the other hand, the transistor 203 is generally called “buried channel transistor” as the gate electrode 612 includes the P-type polysilicon layer and the P-type well region corresponding to nMOSFET structure contains P-type impurities.
The semiconductor device 101 having a surface channel transistor, a buried channel transistor and a transistor with a recess channel structure as described above is well known (see Japanese Patent Application Publication No. 2002-359294).